1. Technical Field
The present invention relates to a stacked memory wherein thin chips are stacked and a specified region in each layer is activated using an address signal which passes through a through electrode in each layer.
2. Related Art
In a stacked memory having components that are high-density mounted by stacking chips, an operation is considered in which a specified region is accessed in a concentrated manner. For example, as shown in FIGS. 1A and 1B, when each layer is simultaneously activated using a common address, if mat regions having a common through electrode are to be activated, there arise unbalanced temperature distributions among the layers, thus causing variations in characteristics accompanied by distortions due to heat and stress differences among the stacked chips. These become significant by making chips further thinner in accordance with requirements for higher integration of memory chips to be stacked as shown in FIG. 1C, and by the increase of operating power that results from higher functionality of the chips.
JP2005-44463A proposes providing a semiconductor device with low power consumption and low heating value by activating memory cells block by block which is a portion of the memory area.